Gradyn Labs

RL environments forchip design

High-difficulty tasks. Robust verifiers. Measured pass rates.

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A single episode runs 20–40 minutes of agent time and ~100 tool calls, with the model running simulation ~10× and full synthesis ~10× as it designs, measures, and improves. The flow is deterministic and identical to grading, so the area and timing the model sees mid-episode are exactly what it's graded on.

20–40 min
agent time / episode
~100
tool calls / episode
~10× · ~10×
simulation · synthesis / run

Built in-house

Every task authored, tested, and quality-assured by our team.

High-difficulty tasks

Multi-step reasoning, complex tool use, and real EDA workflows.

Robust verifiers

Deterministic checks for correctness, functionality, and design constraints.

01 / Thesis

Better models need harder problems.

Frontier models learn from challenging problems with verifiable outcomes. Chip design is unusually rich in this respect: EDA tools provide machine-checkable signals at every stage — compilation, functional equivalence, timing, and design-rule compliance.

We turn these workflows into environments for RLVR. Rewards are grounded in deterministic checks rather than stochastic preferences, across tasks spanning specification, RTL design, verification, and more.

Our team brings years of hands-on chip design and tapeout experience, with five patent applications in progress. That domain expertise shapes the difficulty of our tasks and the reliability of our verifiers.

We focus initially on digital-predominant designs, where verification signals are clearest.

02 / Environments

Environments we generate.

We author original RL environments in-house — we don't license or resell third-party data.

01available

Spec → architecture

Agents turn a product spec into a micro-architecture — partitioning blocks, defining interfaces, and setting performance, latency, and area targets before any RTL is written.

02available

RTL code writing

Agents implement micro-architectural specs in synthesizable HDL — correct, lint-clean, and ready for synthesis.

03available

RTL code verification

Agents write stimulus, triage failures, and raise coverage to prove a design matches its spec.

04available

Synthesis

Agents drive logic synthesis toward clean gate-level netlists under power, performance, and area constraints.

05planned

DFT

Agents insert scan chains and test structures, hitting fault-coverage targets so the manufactured chip stays verifiable.

06planned

Place & route (PnR)

Agents floorplan, place, and route blocks — closing timing and congestion on real physical layouts.

Every environment is built on industry-standard, open-source EDA tools — the same classes used in production flows: a hardware simulator with a programmatic test framework, a logic-synthesis engine, a timing-and-area optimizer, a static-timing signoff tool, and a formal equivalence checker that runs on every submission.

03 / The flow

From spec to silicon.

A chip moves through a long, tool-mediated pipeline. Each stage produces artifacts a machine can check.

  1. 01

    Specification & micro-architecture

    Translate product intent into blocks, interfaces, and performance targets.

  2. 02

    RTL design

    Implement the micro-architecture in synthesizable HDL at register-transfer level.

  3. 03

    Functional verification

    Prove the RTL matches spec with stimulus, coverage, and formal checks.

  4. 04

    Logic synthesis

    Compile RTL into a gate-level netlist mapped to a standard-cell library.

  5. 05

    Place & route

    Place cells and route interconnect on the die; close timing and congestion.

  6. 06

    Signoff

    Check timing (STA), power, and physical rules (DRC/LVS) before manufacturing.

  7. 07

    Tapeout → GDSII

    Export manufacturable GDSII and hand off to the foundry (e.g. TSMC).